Jean-Marie Brunet, Director of Marketing suggested that the largest chips in the world, outside of CPU or GPU are networking chips. In other words, need for verification capacity due to the ever increasing chips sizes and complexity.

“Time to market is essential for leading-edge players in a fast-moving, fast-growing competitive market. They need fast verification at the full-chip level including early software validation.” said Jean-Marie Brunet.

Jean-Marie Brunet said that simulation is insufficient because of limit to cycles per week as well as emulation accelerates the verification process by 1,000,000x over simulation. “Limitations of lab-based environments is another challenge for networking companies. For instance, number of Ethernet ports putting pressure on lab environments, reliability, flexibility and cost.”

The company announced Veloce VirtuaLAB Ethernet support for 25G, 50G and 100G Ethernet that revolutionizing how networking designs ar being verified.

Jean-Marie Brunet stated that networking market rapidly growing and evolving, speed is key to verify highly complex network designs resulted in high capacity needed for huge network designs. “The VirtuaLAB moves emulation from lab to data center with greater reliability, flexibility and lower cost. Along with accessible globally and increasing value of emulation.”