The newly unveiled IP is one of eMemory’s embedded EEPROM NeoEE family. The upgraded NeoEE increases endurance by more than an order and reduces program/erase time by around 50%, with its optimized cell structure and PGM/ERS algorithms.

The enhanced NeoEE is fully compatible with standard logic and Bipolar-CMOS-DMOS (BCD) process without the need for additional masks and process steps. The IP has been silicon verified at 0.18um/5V process, and technology development is underway for other 5V platforms.

The enhanced EEPROM is suitable for applications with high endurance needs such as fingerprint recognition, smart card, NFC, RFID, PMIC and MCU. In particular, the IP is robustly designed and tested to meet AEC-Q100 requirements of high endurance, high temperature and long lifespan.

Repeated PGM/ERS operations compromise reliability of a memory. As the number of rewrite cycles increases beyond a certain limit, the differences between program and erase state would become too small to be recognized, causing endurance failures.

eMemory, with more than a decade of production records for its NVM IPs, has been able to elevate NeoEE’s endurance to over 500K with an innovative cell structure which is able to overcome the window-closing issue caused by repeated rewrite operations.

The new cell structure has been tested and proven reliable at 150°C for 2,500 hours, without charge gain or loss in program/erase state.

NeoEE is a single-poly embedded EEPROM technology, with endurance ranging from 1K to over 500K cycles, bit counts up to 16K bits, and retention for 10years under the operating temperatures between -40°C and 150°C. The IP family provides benefits of minimal implementation costs, low power operation and fast time-to-market.

Originally developed at the standard 5V MOS process platform, NeoEE is easy to be deployed in HV (High Voltage) and BCD platforms tailored to automotive applications.