The DesignWare Duet Packages of Foundation IP include high-speed, area-optimized, and low-power embedded memories, logic libraries built with either standard core oxide or thick IO oxide for ultra-low leakage, STAR Memory System memory test and repair capabilities, and power optimization kits to provide the highest quality of results for an SoC. The DesignWare HPC Design Kit, a suite of high-speed and high-density memory instances and logic cells, enables SoC designers to optimize their CPU, GPU, and DSP cores for an optimum balance of speed, area, and power. The DesignWare OTP NVM IP for TSMC's 22ULP and 22ULL processes does not require additional mask layers or process steps and provides high yields, security, and reliability in a small footprint.

"TSMC and Synopsys share a long track record of successful collaboration to help our mutual customers achieve their SoC performance, power, and area targets," said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. "By offering DesignWare Foundation IP for TSMC's 22ULP and 22ULL processes, Synopsys continues to be a leading provider of proven IP solutions that enable designers to reduce design effort and achieve their design goals on TSMC's latest process technologies."

"Synopsys and TSMC have worked closely through many generations of TSMC process technologies to provide high-quality foundation IP that helps designers meet the power, performance, and area requirements of their SoCs," said John Koeter, vice president of marketing at Synopsys. "Synopsys' DesignWare Logic Library and Embedded Memory IP for TSMC's 22ULP and 22ULL processes enable designers to dramatically reduce power consumption for their target applications and bring differentiated products to market faster."

The DesignWare Duet Packages for TSMC's 22ULP and 22ULL processes and HPC Design Kits for TSMC's 22ULP process are scheduled to be available in Q3 2018. The DesignWare OTP NVM IP is scheduled to be available for 22ULP in Q3 2018, and for 22ULL in Q1 2019.