The silicon-proven Synopsys DesignWare IP for PCIe 3.1 specification incorporates L1 sub-states along with power gating techniques including the utilization of power switches, power islands or retention cells to reduce standby power to less than 10 uW/lane. In addition, supply under drive, a novel transmitter design and equalization bypass schemes cut active power to well below 5 mW/Gb/lane while meeting the PCIe 3.1 electrical specification. By providing a controller and PHY IP solution for PCIe technology that is optimized to deliver the lowest power consumption, Synopsys enables designers to incorporate the necessary functionality into their SoCs and extend the battery life of mobile devices.

The DesignWare PHY IP for PCIe 3.1 technology exceeds required PCIe channel performance with multi-phase-locked loops (MPLLs), Feed Forward Equalization (FFE), Continuous Time Linear Equalization (CTLE) and programmable Decision Feedback Equalization (DFE) to enhance signal integrity across high loss and bumpy channels. Separate Refclk Independent SSC (SRIS), reference clock forwarding and PCI Express architecture aggregation and bifurcation provide flexibility and scalability for high-speed SoCs. The PHY's Automatic Test Equipment (ATE) test capabilities, small area and optional wirebond packaging reduce overall bill of materials (BOM) cost.

As part of the complete solution, the DesignWare Controller IP for PCI Express 3.1 specification supports L1 sub-states in conjunction with power islands or retention cells for up to 95 percent lower leakage power during standby mode and very low exit latency, enabling faster wake up time. To reduce active power, the controller supports system-level power management features including Latency Tolerance Reporting (LTR), Optimized Buffer Flush/Fill (OBFF) and Dynamic Power Allocation (DPA).

In addition, Synopsys Verification IP (VIP) for the PCIe architecture combined with SystemVerilog source code test suites support the validation of low-power scenarios. The VIP provides controls to enter, switch between and exit low-power sub-states. It monitors low-power states, and the test suites provide a dedicated set of tests to validate L1 sub-states functionality.