The combination of the Cadence digital solution with the 16FF+ process provided GUC with a 2X system performance improvement, an 18 percent frequency increase, and a 28% power reduction over their previous design.

GUC utilized the Encounter Digital Implementation System to address the implementation challenges that arise at 16FF+, including increased double-patterning and FinFET design rule checking (DRC), timing and power variability, and throughput requirements.

“As a leader in ASIC designs, we need to deliver very complex designs to our customers in a timely manner, and the Cadence tools and team have helped us do this,” said Jim Lai, president of Global Unichip Corporation.

“We chose to work with Cadence on the development of our design because of their extensive experience with TSMC at advanced nodes. Before we completed our first full production tapeout, we also taped out several 16nm test chips using the Cadence tool set and experienced excellent silicon results. Thanks to the collaboration between the Cadence and GUC teams, we met an aggressive three-month design-to-tapeout schedule for our 180M gate production design.”

“Encounter Digital Implementation System is designed to provide the most effective methodology for 100M+-instance high performance and power-efficient designs,” said Anirudh Devgan, senior vice president, Digital and Signoff Group, Cadence.

“The Encounter system has been validated by TSMC on the 16FF+ process, which gives GUC and other customers the confidence that they can achieve the fastest path to design closure at advanced nodes.”