"Our expanded collaboration with UMC demonstrates our mutual goal to help designers incorporate DesignWare IP into their SoCs on UMC processes," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "With more than 45 FinFET test chip tapeouts, Synopsys continues to make significant investments in providing high-quality IP for FinFET processes, enabling designers to lower integration risk and speed their time to volume production."

"In addition to developing a competitive 14-nanometer process for the most advanced IC applications, UMC is creating a highly comprehensive support infrastructure to accelerate the design-in process for 14-nanometer customers," said Steve Wang, vice president of UMC's IP and Design Support division.

"Following our success with Synopsys on the previous 14-nanometer process qualification vehicle, this collaboration to bring Synopsys' high-quality DesignWare IP to our most advanced node will help our mutual customers realize additional power, performance and cost benefits."