Faraday has for some time offered its AEC (Automotive Electronics Council) standards compliant zero-DPPM solution for automotive applications. Leveraging this know-how, Faraday can now also provide customers with a low-DPPM solution for other applications. During the specification creation stage, the service initiates an overall plan for design, manufacturing and testing to ensure low DPPM target needs.

The ASIC test plan applies testing and monitoring models to confirm that chips meet strict benchmarks at each stage. Finally, multiple analysis and diagnosis methods are employed, such as HVS (high-voltage stress) to detect and screen out early life failures, further enabling low failure rates in the customer’s products.

“Faraday’s low-DPPM solution has been adopted by various industrial and consumer ASIC projects from development to mass production, and it successfully delivers low DPPM results using cost-effective methods,” said Jim Wang, vice president of operations at Faraday. “With more than 26 years of experience in ASIC design service, we continuously optimize our quality management in design, integration, manufacturing, and testing, to provide customers with industry-leading high-quality and high-reliability solutions.”